A Transceiver can be used to provide bidirectional, input or output control, of either digital or analogue devices to a common shared data bus. Unlike the buffer, transceivers are bidirectional devices which allow data to flow through them in either direction.
Thus their name “transceiver” is a portmanteau word coming from the amalgamation of the two words trans-mitter and re-ceive (transmitter/receiver). Transceivers are also known by the names of: send/receive or driver/receiver devices.
In the Digital Buffer Tutorial, we saw that a buffer performs no inversion or decision making capabilities, unlike digital logic gates with two or more inputs, but instead produces an output condition which matches exactly that of its input. Thus a buffer is a “non-inverting” device producing the Boolean expression of: Q = A.
A Digital Buffer like the one shown on the left, is a unidirectional device, that is the signal passes through them in one direction only, from input “A” to the output at “Q“.
Thus, when input A is at logic “1”, output Q is at logic “1”, and when input A is at logic “0”, output Q is at logic “0” for a positive logic device such as the CMOS 74HC4050 Hex Buffer Gate.
Buffers can be used to isolate other gates or circuit stages from each other preventing the impedance or operation of one circuit from affecting the impedance or operation of another. Also on their own, buffers can be used as drivers for high current loads such as transistor switches because their output drive capability (fan-out) is generally much higher than their input signal requirements. For example, the TTL 74LS07 Hex buffer/driver with open collector, high-voltage (30 volts) outputs.
TTL 74LS07 Digital Buffer
The digital non-inverting buffer function can also be made using spare logic AND, or logic OR gates or by using pairs of NOT gates (inverters) as shown.
Equivalent Buffer Designs
One of the disadvantages of a single input digital buffer is that the output at Q will always be at the same logic level as the input possibly affecting whatever circuit or device is connected to the buffers output terminal. One way to overcome this is to turn the basic buffer into a 3-State Buffer, more commonly known as a Tri-state Buffer.
The “Tri-state Buffer”
A Tri-state Buffer is another type of buffer circuit which can be used to control the passage of a logic signal from its input to its output. The tri-state buffer is a combinational device whose output can be electronically turned “ON” or “OFF” by means of an external “Control” or “Enable” (EN) signal input allowing them to be used in bus-orientated systems.
As their name implies, the output at “Q” for a Tri-state Buffer can take on one of three possible states, logic “0”, logic “1”, and High-Z (high impedance), that is, an open circuit, rather than the standard “0” and “1” states.
The buffers enable or control signal can be either a logic “0” or a logic “1” level signal with the output being inverting and non-inverting as the digital signal passes through it. The two most commonly used tri-state buffer IC’s being the TTL 74LS125 and the TTL 74LS126.
Thus a tri-state buffer requires two inputs. One being the data input (A) and the other being the control or Enable input (EN) as shown.
Tri-state Buffer Switch Equivalent
The tri-state buffer’s symbol is very similar to the standard buffer symbol above but with the addition of a second input representing the enable/disable control function. When the enable (EN) input is at a logic level “1” (for positive logic), it acts as a normal buffer allowing the input signal, A to pass directly to the output at Q. Whether it is a logic “0” or a logic “1”.
When the enable input is at logic “0”, the tristate buffer is activated into its third state and disables or turns “OFF” its output producing an open circuit condition. This third condition is neither at a logic “1” (high) or logic “0” (low), but instead gives an output state that is at a very high impedance, High-Z, more commonly written as: Hi-Z.
Thus a tri-state buffer has two logic state inputs, “0” or a “1” but can produce three different output states, “0”, “1” or “Hi-Z” which is why it is called a “Tri” or “3-state” device. Note that this third state is NOT equal to a logic level “0” or a “1”, but is an high impedance state as its output is electrically disconnected.
Then we can correctly state for a positively enabled tri-state buffer that:
- If the enable signal is HIGH, logic “1”, the input signal of the buffer gate is passed directly to its output.
- If the enable signal is LOW, logic “0”, the output of the buffer gate acts like an open circuit, that is, high impedance, (Hi-Z).
and we can present the truth table for a tri-state buffer as:
Active “HIGH” Tri-state Buffer
Tri-state Buffers are available in integrated form as quad, hex or octal buffer/drivers such as the TTL 74LS244 as shown.
74LS244 Octal Tri-state Buffer
Notice that the eight buffers are configured into two groups of four with the first group (A1 to A4) being controlled by enable input, CA, and the second group (A5 to A8) being controlled by the enable input, CB. The 74LS244 has very high sink and source current capabilities if required to switch transistor loads.
Tri-state Buffer Control
So what can we use a 3-state or tri-state buffer for. Tri-state buffers can allow multiple devices to share a common output wire or bus by having only one tri-state device drive the wire bus at any one time while all other buffers remain in their Hi-Z state. Consider the circuit below.
Multiple tri-state buffers on a single Bus
The outputs from each tri-state buffer are connected to a common wire bus but their enable inputs are connected to a binary decoder. The decoder guarantees that only one tri-state buffer will be active at any one time, due to its enable signal.
This allows the data of the active buffer to pass directly onto the common bus while the outputs of the other non-enabled buffers are effectively disconnected and in their high-impedance state. Thus which buffer is connected to the common line will depending on the binary value of the decoders select inputs.
Therefore, no more than one tri-state buffer can be in an “active state” at any given time. You may have noticed that the possible combination of different data inputs connected to a single output line above resembles that of a 4-to-1 line multiplexer, and you would be right, multiplexer circuits can be easily constructed using tri-state buffers.
Any tri-state buffer element can easily be converted into a normal digital buffer by simply connecting their enable (EN) input directly to +Vcc or ground, depending on the tri-state buffer used. Thus, the output is permanently enabled so any input signal present at “A” will pass straight through the buffer to the output at “Q“.
We have seen thus far, that we can use tri-state buffers to send information in a uni-directional way onto a common wire or bus. But how could we use them to send data in both directions, that is, to send data too and receive data from a common wire bus.
Bi-directional Buffer Control
It is also possible to connect Tri-state Buffers “back-to-back” (inverse parallel) to produce what is called a Bi-directional Buffer or transceiver circuit. By using an additional inverter, one tri-state buffer is as an “active-high buffer”, while the other operates as an “active-low buffer”, as shown.
Multiple tri-state buffers on a single Bus
Here, the two tri-state buffers are connected in parallel but in reverse from “A” to “B” with the enable control input, EN acting more like a directional control signal thus allowing data to be both read “from” and transmitted “to” the same data terminal.
So in this simple example, when the enable input is HIGH, (EN equals logic “1”) data is allowed to pass from A to B via buffer 1, and when the enable input is LOW, (EN equals logic “0”) data passes from B to A via buffer 2.
Thus the enable input “EN” acts as direction control allowing data to flow in either direction depending upon the logic status of this control input. In this type of application a tri-state buffer with bi-directional switching capability such as the TTL 74LS245 or the inverting CMOS 74ALS620 can be used producing what is called a Bus Transceiver.
Bus transceivers are tri-state bi-directional devices which allow the flow of data between two points making them compatible with bus-oriented systems or the bi-directional (input or output) control of interface circuitry. Bus transceivers can be inverting, the TTL 74LS242 or non-inverting, the TTL 74LS243 devices.
Thus we can use an 8-line octal transceiver to interface any input/output device to an 8-bit data bus with the most common bus transceiver IC being used to both send and receive data is the TTL 74LS245 given below.
74LS245 Bus Transceiver
The TTL 74LS245 is an octal bus transceiver (Transmitter/Receiver) designed for asynchronous two-way communication between two data buses or input/output device. The transceiver allows for the transmission of data from the terminals A to terminals B or the reverse depending on the logic level at the direction-control (DIR) input, (pin 1).
So for example, if the direction-control input is HIGH at logic level “1”, then data will pass from terminal set A to terminal set B. If the direction-control input is LOW at logic level “0”, then data will pass in the reverse direction from terminal set B to terminal set A.
So when held HIGH at logic level “1”, the output chip-enable (CE) input, (pin 19) can be used to disable the device so that the terminals, and therefore any connected data buses are effectively isolated from each other in a Hi-Z state.