The Toggle Flip-flop is another type of bistable sequential logic circuit based around the previous clocked JK flip-flop circuit. The toggle flip-flop can be used as a basic digital element for storing one bit of information, as a divide-by-two divider or as a counter. Toggle flip-flops have a single input and one or two complementary outputs of Q and Q which change state on the positive edge (rising edge) or negative edge (falling edge) of an input clock signal or pulse.
Toggle flip-flops, TFF’s or simply “T-type flip-flops” are not available commercially as a dedicated TTL or CMOS logic chip, they can be easily constructed by connecting together the J and K inputs of a basic JK flip-flop where the J input behaves like a Set (S) command, and the K input behaves like a Reset (R) command. We remember from our previous tutorial that the JK flip-flop is an asynchronous flip-flop where its input condition (HIGH or LOW), and its present steady state, both determine its next switching state.
The JK Flip-flop can be classed as a “universal” flip-flop because it can be configured and used to replicate the switching action of other types of flip-flops depending on the logical states applied to its J and K inputs. But before we look at T-type flip-flops in more detail, let’s first remind ourselves of the basic JK flip-flop circuit and switching action.
Basic JK Flip-flop Circuit using NAND Gates
The circuit above shows the basic configuration of a JK flip-flop using four NAND gates, but they could also be constructed using NOR gates. The JK flip-flop has three inputs labelled J, K, and the clock (CLK). The data input J, (which corresponds to Set) is applied along with the feedback from Q to the upper 3-input NAND gate, while the other data input K, (which corresponds to Reset) and the Q feedback connection are applied to the lower 3-input NAND gate.
If inputs J and K are both LOW, (J = K = 0), then there will be no change in Q no matter how many times the clock pulse is applied. If J = 0 (LOW) and K = 1 (HIGH) the next clock edge resets Q output LOW (Q = 0). If J = 1 and K = 0, then the next clock edge sets Q output HIGH (Q = 1).
Characteristics Table for the JK Function
| CLK | J | K | Q | Q+1 | Action |
| 0 | X | X | 0 | 0 | Not allowed |
| _↑¯ | 0 | 0 | 0 | 0 | No change |
| _↑¯ | 0 | 0 | 1 | 1 | |
| _↑¯ | 0 | 1 | 0 | 0 | Reset |
| _↑¯ | 0 | 1 | 1 | 0 | |
| _↑¯ | 1 | 0 | 0 | 1 | Set |
| _↑¯ | 1 | 0 | 1 | 1 | |
| _↑¯ | 1 | 1 | 0 | 1 | Toggle |
| _↑¯ | 1 | 1 | 1 | 0 |
Where: X means “don’t care”, a “0” or a “1”, and _↑¯ is the positive rising-edge of the clock pulse.
Then we can define this switching action in Boolean form as being:
Q+1 = J.K.Q + J.K.Q + J.K.Q + J.K.Q
Q+1 = K.Q(J+J) + JQ(K+K)
Q+1 = K.Q + J.Q
Where: Q represents the present steady state of the flip-flop and Q+1 is the next switching state.
The problem here is that if both the J and K data inputs are at logic “1”, HIGH at the same time (J = K = 1), when the clock (CLK) input goes HIGH, its outputs switch and change state complementing each other. But as the outputs are fed back, the outputs will change state continuously after being complemented once, causing the output at Q to oscillate between set and reset. So JK flip-flops are not built using the basic NAND or NOR gate configurations as shown but instead are constructed to form more advanced master-slave (edge-triggered) flip-flops which are more stable.
Toggle Flip-flop
While the Data (D) flip-flop is a variation of a clocked SR flip-flop constructed using either NAND or NOR gates, the Toggle (T) flip-flop is a variation of the clocked JK flip-flop. The toggle or T-type flip-flop gets its name from the fact that its two outputs Q and Q invert from their previous state as it toggles back and forth every time it is triggered (T = 1).
That is, the Q and Q outputs change to a “1” if it was “0”, and “0” if it was previously a “1” but only when the “T” input changes HIGH, otherwise they do not change, and its this asynchronous toggling action we are interested in here.
The JK is renamed T for T-type or Toggle flip-flop and is generally represented by the logic or graphical symbol shown. The Toggle schematic symbol has two inputs available, one represents the “toggle” (T) input and the other the “clock” (CLK) input.
Also, just like the 74LS73 JK flip-flop, the T-type can also be configured to have an enable input called EN or CE (clock enable) allowing it to hold the last data state stored on its outputs indefinately. Thus with the clock enable input set, the application of any new clock pulses prevents toggling of the outputs. But this “enable” feature, if required, must be implimented using additional logic gates.
The triangle of chevron on the input of either type of T-type flip-flop indicates that it is an edge-triggered device. If there is a small bubble or circle at the input, then it indicates that the flip-flop toggles on the negative falling edge (HIGH-to-LOW) of each pulse, otherwise, it changes state on the positive or rising transistional edge (LOW-to-HIGH) of each input pulse.
Then we can create the logic circuit of a single bit toggle flip-flop using the basic JK flip-flop by connecting the J and K data inputs together where the common point at the connection of the two inputs is designated T, as shown.
The Toggle Flip-flop
Suppose that initially CLK and input T are both LOW (CLK = T = 0), and that output Q is HIGH (Q = 1). At the rising edge or falling edge of a CLK pulse, the logic “0” condition present at T prevents the output at Q from changing state. Thus the output remains unchanged when T = 0.
Now let’s suppose that input T is HIGH (T = 1) and CLK is LOW (CLK = 0). At the rising edge (assuming positive transistion) of a CLK pulse at time t1, the output at Q changes state and becomes LOW, making Q HIGH. The negative transistion of the clock pulse from HIGH to LOW at time t2 has no effect on the output at Q as the flip-flop is reset into one stable state.
At the next rising edge of the clock signal at time t3, the logic “1” at T passes to Q, changing its state making output Q HIGH again. The negative transistion of the CLK pulse at time t4 from HIGH to LOW once again has no effect on the output. Thus the Q output of the flip-flop “toggles” at each positive going edge (for this example) of the CLK pulse.
Characteristics Table for the Toggle Function
| CLK | T | Q | Q+1 |
| _↑¯ | 0 | 0 | 0 |
| _↑¯ | 0 | 1 | 1 |
| _↑¯ | 1 | 0 | 1 |
| _↑¯ | 1 | 1 | 0 |
Then we can define the switching action of the toggle flip-flop in Boolean form as being:
Q+1 = T.Q + T.Q
Where: Q represents the present steady state of the flip-flop and Q+1 is the next switching state.
You may have noticed that the characteristic equation given in Boolean form for the toggle flip-flop above will produce an output HIGH for the next state (Q+1) if the two inputs of T and Q are different, and a LOW output if these inputs are the same.
This idea of Q+1 is HIGH only when either of the inputs is HIGH but not when both inputs are HIGH, that is either input but not both represents the same Boolean Algebra expression of an Exclusive-OR Function which is given as:
Q+1 = TQ + TQ = T XOR Q = T ⊕ Q
Then we can represent the switching action of a toggle flip-flop using a 2-input Exclusive-OR (Ex-OR) gate.
Conversion of JK Flip-flop into D-type Flip-flop
As well as bistable JK flip-flop’s, we can also produce a toggling action using D-type or Delay flip-flop’s constructed from a simple modification of a clocked JK circuit. The D-type flip-flop has two inputs, D (Data) and CLK (Clock) and changes state in response to a positive or negative edge transition on the clock input. The D-type flip-flop can also be used to provide temporary storage of one bit of information the same as the toggle flip-flop.
Conversion of JK Flip-flop into D-type Flip-flop
The addition of an inverter (NOT gate) between the J and K terminals and replacing them with just one input D (for data). This means that they can never have the same digital value because if input J = 0, then K = 1, likewise if J = 1, then K = 0. The advantage here is that the inclusion of the inverter between J and K results in the output value at Q following the D input value (0 or 1) whenever the clock (Clk) is HIGH, logic “1” and we can show this in the switching table below.
Characteristics Table for the D-type Function
| CLK | D | Q | Q+1 | Action |
| _↑¯ | 0 | 0 | 0 | Reset |
| _↑¯ | 1 | 1 | 1 | Set |
where Q is the present state and Q+1 is the next state after the application of a single clock pulse. Then we can define the switching action of the D-type flip-flop in Boolean form as being:
Q+1 = D
Thus the steady state condition of its output only toggles HIGH or LOW each time its clock input is pulsed, if and only if there is a change to the data input (D). That is the D-type flip-flop configuration only allows the output at Q to have the same steady state condition as the D input when clocked HIGH. The disadvantage here is that we need two separate inputs, D and Clk to make it toggle. Then we need a way of making its Q output change to the opposite state, that is toggle, with the application of each clock pulse.
Conversion of D-type Flip-flop into Toggle Flip-flop
We saw above that the boolean expression given for the switching action of a toggle flip-flop can represent that of an exclusive-OR gate as Q+1 = Q ⊕ T. Then we can add an exclusive-OR logic gate to convert the given D-type flip-flop into a T-type flip-flop as shown.
Conversion of D-type Flip-flop into T-type Flip-flop
Characteristics Table for the Toggle Flip-flop
| CLK | T | Q | Q+1 | Action |
| _↑¯ | 0 | 0 | 0 | No change |
| _↑¯ | 1 | 1 | 0 | Toggle |
| _↑¯ | 1 | 0 | 1 |
Here, “T” becomes one of the inputs of a 2-input exclusive-OR gate while output Q is fed back to become the other. Thus T and Q are both inputs to the Ex-OR gate to produce the required Boolean expression to drive the D input. If T = 0, the output of the exclusive-OR gate which is Q ⊕ T will also be LOW (0), so the D-type flip-flop stays fixed in one stable state.
However, when T = 1, the exclusive-OR produces a change of state at D every time the D-type flip-flop is clocked as the output Q which is fed back to the gate toggles between HIGH and LOW on every clock pulse, making it very useful as a bistable element when a single data bit is to be stored.
As this configuration can only hold its unchanged state, or the complement its state, there is no way to establish an initial output state either HIGH or LOW when power is first applied without adding additional Preset (Pre) or Clear (Clr) inputs or external circuitry to initialise or set the output Q to a known state.
Also, since the output at Q changes state on the rising edge of each and every clock pulse, the time period of the output at Q will be equal to half the frequency of the clock pulse. That is the T-type flip-flop’s toggling action creates a divide-by-two circuit who’s output has a 1:1 (50%) Mark-to-Space ratio as the LOW period and HIGH period of the Q output are of equal length. This means that toggle flip-flops are very useful as simple binary counters or ripple counters for frequency division (reducing the frequency of a periodic waveform) in which of “n” toggle flip-flop stages are connected together in series.
