The analogue switch is a solid-state semiconductor switch that controls the transmission path of analogue signals. The open and closed operations of the switch positions are usually controlled by some digital logic network, with standard analogue switches available in many styles and configurations. For example, single or dual normally open (NO) or normally closed (NC), single-pole single-throw (SPST), single-pole, double-throw (SPDT) configurations etc, in much the same way as for conventional electromechanical relays and contacts.
The switching and routing of digital and analogue signals (both voltage and current) can easily be done using mechanical relays and their contacts, but these can be slow and costly. The obvious choice is to use much faster acting solid state electronic switches which use metal oxide semiconductor (MOS) analogue gates to route the signal currents from their input to their output, with the well-known CMOS 4016B bilateral switch being the most common example.
MOS technology uses both NMOS and PMOS devices to perform the logical switching functions, thus allowing a digital computer or logic circuit to control the operation of these analogue switches. CMOS devices where both NMOS and PMOS transistors are fabricated into the same gate circuit, can pass (closed-condition) or block (open-condition) an analogue or digital signal, depending on the digital logic level that controls it.
The type of solid-state switch which allows for a signal or data transfer in both directions is called a Transmission Gate, or TG. But first lets consider the operation of a Field Effect Transistor, or FET as a basic analogue switch.
The MOSFET as an Analogue Switch
Both Bipolar Junction Transistors (BJTs) and Field Effect Transistors (FETs) can be used as a single-pole electronic switch in a wide variety of different applications. The main advantages of MOSFET, or metal-oxide-semiconductor FET, technology over bipolar devices is that its gate terminal is insulated from the main conducting channel by a thin layer of metal oxide, and the main MOSFET channel used for switching is purely resistive.
Consider the basic N-channel and P-channel enhancement MOSFET (eMOSFET) configurations below.
The MOSFET as a Switch
Then we can see that for the n-channel (NMOS) and p-channel (PMOS) enhancement MOSFET to operate as an open (OFF) or closed (ON) device the following conditions must be true:
- An N-channel MOSFET behaves like an closed switch when the gate-source voltage, VGS is greater than the threshold voltage, VT. That is VGS > VT
- An N-channel MOSFET behaves like an open switch when the gate-source voltage, VGS is less than the threshold voltage, VT. That is VGS < VT
- A P-channel MOSFET behaves like an closed switch when the gate-drain voltage, VGD is less than the threshold voltage, VT. That is VGD < VT
- A P-channel MOSFET behaves like an open switch when the gate-drain voltage, VGD is greater than the threshold voltage, VT. That is VGD > VT
Note that a MOSFETs Threshold Voltage, VT is the minimum voltage applied to the gate terminal for the main channel between the drain and source terminals to start conducting. Also, since the eMOSFET is used mainly as a switching device, it generally operates between its cut-off and saturation regions thus VGS acts as an ON/OFF control voltage for the MOSFET.
The Ideal Switch
An ideal analogue switch would create a short-circuit condition when closed and an open-circuit condition when open, in a similar fashion to a mechanical switch.
However, solid-state analogue switches are not ideal as there is always some loss associated with the conducting channel due to its resistive value when ON.
We would like to think that if we applied a signal to its input pin this would result in the signal being identical and without loss at the output pin, and vice versa. However, while CMOS switches do make excellent transmission gates, their “ON” state resistance, RON can be several ohms creating an I2*R power loss, while their “OFF” state resistance can be several thousand ohms allowing pico amperes of current to still flow through the channel.
Nevertheless, the ability of complementary metal-oxide semiconductor FETs to perform as analogue switches and transmission gates remains high, and MOSFET devices, in particular the enhancement MOSFET which requires a voltage to be applied to the gate to turn it “ON” and zero voltage to turn it “OFF” are the most commonly used switching transistor.
The NMOS Switch
The N-channel metal-oxide semiconductor (NMOS) transistor can be used as a transmission gate for the passing of analogue signals. Assuming that the drain and source terminals are identical, the input is connected to the Drain terminal and the control signal to the gate terminal as shown.
NMOS FET as an Analogue Switch
When the control voltage, VC on the gate is zero (LOW), the gate terminal will not be positive with respect to either input terminal (drain) or the output terminal (source), thus the transistor is in its cut-off region and the input and output terminals are isolated from each. Then the NMOS is acting an open switch so any voltage at the input will not be passed to the output.
When there is a positive control voltage +VC at the gate terminal, the transistor is turned “ON” and in its saturation region acting as a closed switch. If the input voltage, VIN is positive and greater than VC current will flow from the drain terminal to the source terminal, thus connecting VOUT to VIN.
If however VIN becomes zero (LOW) while the gates control voltage is still positive, the transistor channel is still open but the drain-to-source voltage, VDS is zero, so no drain current flows through the channel and thus the output voltage is zero.
Therefore, as long as the gate control voltage, VC is HIGH, the NMOS transistor passes the input voltage to the output. If it is LOW, the NMOS transistor is turned “OFF”, and the output terminal is disconnected from the input. Thus, the control voltage, VC at the gate determines whether the transistor is an “open” or “closed” as a switch.
One issue here with the NMOS switch is that the gate-to-source voltage, VGS must be significantly greater than the channel threshold voltage to turn it fully-ON or there will be a voltage reduction through the channel. Thus the NMOS device can only transmit a “weak” logic “1” (HIGH) level but a strong logic “0” (LOW) without loss.
The PMOS Switch
The P-channel metal-oxide semiconductor (PMOS) transistor is similar but opposite in polarity to the previous NMOS device with current flowing in the opposite direction, from source to drain. Then for a PMOS device, the input is connected to the Source terminal and the control signal to the gate terminal as shown.
PMOS FET as a Switch
For the PMOS FET, when the control voltage, VC on the gate is zero and is thus more negative with respect to either input terminal (source) or the output terminal (drain), the transistor is “ON” and in its saturation region acting as a closed switch. If the input voltage, VIN is positive and greater than VC current will flow from the source terminal to the drain terminal, that is ID flows out of the drain thus connecting VIN to VOUT.
If the input voltage, VIN becomes zero (LOW) while the gates control voltage is still zero or negative, the PMOS channel is still open but the source-to-drain voltage, VSD is zero, so no current flows through the channel and thus the voltage at the output (drain) is zero.
When there is a positive control voltage +VC at the gate terminal, the channel of the PMOS transistor is turned “OFF” and in its cut-off region acting as a open switch. Thus no drain current, ID flows through the conducting channel.
Therefore, as long as the gate control voltage, VC is LOW (or negative), the PMOS transistor will pass the input voltage to the output. If it is HIGH, the PMOS transistor is turned “OFF”, and the output terminal is disconnected from the input. Thus as with the previous NMOS device, the control voltage, VC at the gate determines whether the transistor is an “open” or “closed” as a switch.
The problem with the PMOS switch is that the gate-to-source voltage, VGS must be significantly less than the channel threshold voltage to turn it fully-OFF or current will still flow through the channel. Thus the PMOS device can transmit a “strong” logic “1” (HIGH) level without loss but a weak logic “0” (LOW).
So we can see that for an NMOS device a positive gate-to-source voltage causes current to flow in one direction from Drain-to-Source, while for the PMOS device, a negative gate-to-source voltage will result in current flowing in the reverse direction from Source-to-Drain.
However, the NMOS device only passes a strong “0” but a weak “1”, while the PMOS device passes a strong “1” but a weak “0”. Thus by combining the characteristics of the NMOS and the PMOS devices, it is possible to transmit both a strong logic “0” or a strong logic “1” value in either direction without any degradation. This then forms the basis of a Transmission Gate.
Transmission Gate
Connecting PMOS and NMOS devices together in parallel we can create a basic bilateral CMOS switch, known commonly as a “Transmission Gate”. Note that transmission gates are quite different from conventional CMOS logic gates as the transmission gate is symmetrical, or bilateral, that is, the input and output are interchangeable. This bilateral operation is shown in the transmission gate symbol below which shows two superimposed triangles pointing in opposite directions to indicate the two signal directions.
CMOS Transmission Gate
Two MOS transistors are connected back-to-back in parallel with an inverter used between the gate of the NMOS and PMOS to provide the two complementary control voltages. When the input control signal, VC is LOW, both the NMOS and PMOS transistors are cut-off and the switch is open. When VC is high, both devices are biased into conduction and the switch is closed.
Thus the transmission gate acts as a “closed” switch when VC = 1, while the gate acts as an “open” switch when VC = 0 operating as a voltage-controlled switch. The bubble of the symbol indicating the gate of the PMOS FET.
Transmission Gate Boolean Expression
As with traditional logic gates, we can define the operation of a transmission gate using both a truth table and boolean expression as follows.
Transmission Gate Truth Table
| Symbol | Truth Table | ||
Transmission Gate
|
Control | A | B |
| 1 | 0 | 0 | |
| 1 | 1 | 1 | |
| 0 | 0 | Hi-Z | |
| 0 | 1 | Hi-Z | |
| Boolean Expression B = A.Control | Read as A AND Cont. gives B | ||
We can see from the above truth table, that the output at B relies not only the logic level of the input A, but also on the logic level present on the control input. Thus the logic level value of B is defined as both A AND Control giving us the boolean expression for a transmission gate of:
B = A.Control
Since the boolean expression of a transmission gate incorporates the logical AND function, it is therefore possible to implement this operation using a standard 2-input AND gate with one input being the data input while the other is the control input as shown.
AND Gate Implementation
One other point to consider about transmission gates, a single NMOS or a single PMOS on its own can be used as a CMOS switch, but the combination of the two transistors in parallel has some advantages. An FET channel is resistive so the ON-resistances of both transistors are effectively connected in parallel.
As a FETs On-resistance is a function of the gate-to-source voltage, VGS, as one transistor becomes less conducting due to the gate drive, the other transistor takes over and becomes more conducting. Thus the combined value of the two ON-resistances (as low as 2 or 3Ω) stays more or less constant than would be the case for a single switching transistor on its own.
When can demonstrate this in the following diagram.
Transmission Gate ON-resistance
Transmission Gate Summary
We have seen here that connecting a P-channel FET (PMOS) with an N-channel FET (NMOS) we can create a solid-state switch which is digitally controlled using logic level voltages and is commonly called a “transmission gate”.
The Transmission Gate, (TG) is a bilateral switch where either of its terminals can be the input or the output. As well as the input and output terminals, the transmission gate has a third connection called the control, where the control input determines the switching state of the gate as an open or closed (NO/NC) switch.
This input is typically driven by a digital logic signal that toggles between ground (0V) and a set DC voltage, usually VDD. When the control input is low (Control = 0), the switch is open, and when the control input is HIGH (Control = 1) the switch is closed.
Transmission gates act like voltage-controlled switches, and being switches, CMOS transmission gates can be used for switching both analogue and digital signals passing the full range of voltages (from 0V to VDD) in either direction, which as discussed is not possible with a single MOS device.
The combination of an NMOS and a PMOS transistor together within a single gate means that the NMOS transistor will transfer a good logic “0” but a poor logic “1”, while the PMOS transistor transfers a good logic “1” but a poor logic “0”. Therefore, connecting an NMOS transistor with a PMOS transistor in parallel provides a single bilateral switch which offers efficient output drive capability for CMOS logic gates controlled by a single input logic level.
